53 件 ・ 関連度順
概要と使いどころ
Develop Lakeflow Spark Declarative Pipelines (formerly Delta Live Tables) on Databricks. Use when building batch or streaming data pipelines with Python or SQL, including Auto CDC from event streams or periodic complete snapshots. Invoke BEFORE starting implementation.
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Build managed ingestion pipelines into Databricks using Lakeflow Connect. Use when ingesting from SaaS apps (Salesforce, Workday Reports, ServiceNow, Google Analytics 4, HubSpot, Confluence) or databases (SQL Server cloud and on-prem; PostgreSQL/MySQL CDC in PuPr) into Unity Catalog with serverless pipelines.
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Think and work like an expert Medical Parasitologist. Use when a task calls for Medical Parasitologist judgment. Reasons from specimen-stage fit, exposure-based pretest probability, and antigen-versus-antibody kinetics through thick/thin Giemsa films, formalin-ethyl-acetate concentration with trichrome, multiplex PCR, and EITB serology against CDC DPDx and WHO algorithms, while treating pfhrp2/3-deleted RDT false-negatives, single-O&P misses of Strongyloides, and colonization-mistaken-for-infection as first-class failure modes.
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Think and work like an expert FPGA Engineer. Use when a task calls for FPGA Engineer judgment. Reasons from metastability budgets, setup/hold margins, and tool-reported WNS/TNS through Vivado/Quartus timing and CDC reports, XDC/SDC constraints, Spyglass/Verilator lint, and ILA/IBERT lab bring-up while treating unsafe clock-domain crossings, reset domain crossings, sim-versus-silicon X mismatches, and unconstrained timing paths as first-class failure modes.
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Think and work like an expert Computer Hardware Engineer. Use when a task calls for Computer Hardware Engineer judgment. Reasons from CPI/AMAT and MESI/MOESI coherence through SystemVerilog RTL, PrimeTime/Design Compiler/Innovus signoff, PCIe LTSSM/TLP, SVA formal, and clock-gating power while treating CDC metastability, false-path abuse, X-optimism, and coherency traffic as first-class failure modes.
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Think and work like an expert Data Engineer. Use when a task calls for Data Engineer judgment. Reasons from idempotent ELT, medallion bronze/silver/gold, Kimball grain and SCD2, CDC/Debezium and watermark incremental loads, dbt/GX quality gates, Airflow/Dagster orchestration, Iceberg/Delta lakehouse MERGE, data contracts and freshness SLIs while treating silent join drops, duplicate amplification, schema drift, and green-DAG-wrong-numbers as first-class failure modes.
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You are an expert in Airbyte, the open-source data integration platform with 300+ pre-built connectors. You help developers sync data from SaaS tools, databases, and APIs into data warehouses and lakes — handling incremental syncs, CDC (Change Data Capture), schema evolution, and error recovery for production data pipelines.
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Build and configure a GraphQL API backed by Neo4j using @neo4j/graphql v7 (current) or v5 (LTS). Covers Neo4jGraphQL constructor, getSchema(), assertIndexesAndConstraints(), type definitions with @node, @relationship (IN/OUT/UNDIRECTED), @cypher for custom resolvers, @authorization/@authentication for JWT/JWKS security, auto-generated queries/mutations, OGM programmatic access, subscriptions via CDC, and Apollo Federation. Use when writing typeDefs, securing fields, or wiring Neo4j to Apollo Server. Does NOT handle raw Cypher outside resolvers — use neo4j-cypher-skill. Does NOT cover Spring Data Neo4j entity mapping — use neo4j-spring-data-skill.
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Designs lakehouse platforms across Iceberg, Delta, Hudi, and Paimon. Use when choosing catalogs, CDC paths, query engines, governance, or cost controls.
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Manage construction contract administration from the field perspective. Covers AIA contract forms (A101, A201, A401), bond types and requirements, mechanics lien law, insurance verification, indemnification, dispute resolution, and subcontractor default procedures. Provides practical field guidance for notice requirements, lien waiver processing, COI verification, and claims documentation. Integrates with pay-application (lien waivers), change-order-tracker (constructive changes), delay-tracker (notice provisions), sub-performance (default triggers), and cost-tracking (back-charges). Triggers: "contract", "contract admin", "AIA", "A201", "A101", "bond", "performance bond", "payment bond", "lien", "lien waiver", "mechanics lien", "insurance", "COI", "certificate of insurance", "OCIP", "CCIP", "indemnification", "dispute", "mediation", "arbitration", "notice", "cure notice", "default", "sub default", "termination for cause", "claims", "ConsensusDocs", "EJCDC".
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USB and CAN connectivity for Zephyr RTOS. Covers USB device stack configuration (CDC ACM, HID, MSC), CAN controller integration, and professional USB-to-CAN adapter patterns including buffering and protocol packetization. Trigger when adding USB interfaces, implementing CAN bus communication, or building hardware diagnostic tools.
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调用 Yosys 0.35 对 RTL 进行逻辑综合并技术映射到 ASAP7 标准单元，产出门级网表 + QoR 报告。支持并行综合（基于空闲CPU数量）。Workflow: (1)生成综合脚本;(2)并行执行综合;(3)LLM检查结果并迭代优化。触发场景：(1) bba-guru-synthesis 已完成 SDC 与 CDC 检查、需要生成 netlist；(2) PD 反馈 area/path 超标需要重综合；(3) 显式 /bb-invoke-yosys。
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Data migration and synchronization to SurrealDB from MongoDB, PostgreSQL, MySQL, Neo4j, Kafka, and JSONL. Full and incremental CDC sync. Part of the surreal-skills collection.
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Use this skill to select the right Salesforce integration pattern — from point-to-point to event-driven to hub-and-spoke — by applying the official Salesforce two-axis decision framework (integration type × timing) to a business integration scenario. Trigger keywords: integration pattern decision, choose integration approach, Salesforce integration architecture, when to use platform events vs API, integration type selection. NOT for implementation of any specific integration pattern (use domain-specific integration skills), MuleSoft architecture (use architect/mulesoft-anypoint-architecture), or middleware vendor selection. More triggers: integration decision record, Bulk API vs REST for a nightly load, external Id upsert, Named Credential vs Remote Site Setting, platform event vs CDC, who calls whom.
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Router for the 61 SfSkills `integration` skill packages. INBOUND integration and the API surface itself: the Salesforce REST and SOAP APIs, Bulk API 2.0 jobs, Platform Events, CDC, Pub/Sub, Named Credentials and middleware. For calling OUT to someone else's API from Apex, use salesforce-apex instead. Use when the request mentions integration, Salesforce REST API, composite API, SOAP API, Bulk API 2.0 job, Platform Event, Change Data Capture, Pub/Sub, inbound webhook, Named Credential, OAuth, connected app, MuleSoft, Salesforce Connect, external system calling Salesforce. Finds and opens the exact skill package to read; it does not contain the guidance itself.
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Install, configure, and work with Turso DB — an in-process SQLite-compatible relational database engine written in Rust. Use when the user needs to (1) install Turso DB, (2) create or query databases with the tursodb CLI shell, (3) use Turso from JavaScript/Node.js via @tursodatabase/database, (4) work with vector search or embeddings in Turso, (5) set up full-text search with FTS indexes, (6) configure transactions including MVCC concurrent transactions, (7) enable encryption at rest, or (8) use Change Data Capture (CDC) for audit logging.
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Audit public sector and government resource allocation systems for budget optimization algorithms (zero-based, incremental, performance-based), service demand forecasting (ARIMA, Prophet, regression), equity-based distribution scoring (CDC SVI, environmental justice indices.
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Firmware development for the Beetle — the CJMCU / DFRobot "Mini Arduino Leonardo" USB board (ATmega32U4 @ 16 MHz, 5 V, 21×28 mm, castellated pads) — its native USB (CDC serial + HID keyboard/mouse/joystick), Caterina bootloader and 1200 bps touch upload, ten exposed I/O pads, four PWM pins across Timer0/Timer1, five ADC channels, I2C on D2/D3, SPI on the back-side ICSP pads, 28 KB usable flash and 2.5 KB SRAM, and the PlatformIO + Arduino AVR core (`board = leonardo`) setup around them. Use when working on this board or any ATmega32U4 Leonardo/Micro/Pro-Micro-class clone: project setup, platformio.ini, why the board shows up as two different serial ports, uploads that fail or hang, recovering a bricked or HID-spamming board by shorting the ICSP reset pads, pin mapping and which pads are missing, PWM/timer conflicts, Servo and tone, USB HID keyboard projects, the SRAM budget, powering from the + pad, or debugging why something on the board does not work.
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Firmware development for the WeAct Studio "Black Pill" (STM32F411CEU6) and its clones such as the DFRobot DFR0864 — the 25 MHz HSE and 32.768 kHz LSE crystals, PC13 LED, K1 button, USB-C wired straight to USB_OTG_FS, ROM DFU flashing, the SPI-flash footprint, and the STM32Cube HAL + PlatformIO setup around them. Use when working on this board or any STM32F411CE/F401CC Black Pill: project setup, platformio.ini, clock and PLL configuration for 96 MHz plus 48 MHz USB, pin mapping on the 48-pin package, USB CDC console, RTC on the LSE crystal, the internal temperature sensor, ADC accuracy, DFU flashing and recovery, or debugging why something on the board does not work.
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Firmware development for the WeAct Studio RP2350A Core Board (RP2350A — dual Cortex-M33 @ 150 MHz, 520 KB SRAM, 4 MB or 16 MB QSPI flash) in both of its revisions, RP2350A_V10 and RP2350A_V20 — the 40-pin Pico-2-shaped header, 3-or-4-channel 12-bit ADC, PWM, PIO, USB-C CDC, the V1.0 LDO vs V2.0 buck-boost power wiring, and the PlatformIO + arduino-pico (earlephilhower) setup around them. Use when working on this board, a WeAct RP2350 core board of unknown revision, or any Raspberry Pi Pico 2 / RP2350A clone: project setup, platformio.ini, board = rpipico2 vs weact_rp2350b, telling V1.0 and V2.0 apart, pin mapping, LED and KEY pins, powering it from a battery, 4 MB vs 16 MB flash, erratum RP2350-E9 pull-down trouble, BOOT/RESET UF2 flashing, or debugging why something on the board does not work.
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Firmware development for the ProMicro nRF52840 (V1940) — the nice!nano v2 compatible clone also sold as SuperMini nRF52840, nRF52840 Pro Micro or nRFMicro (nRF52840 QIAA, Cortex-M4F @ 64 MHz, 1 MB flash / 256 KB RAM, BLE 5 + 802.15.4, native USB, Adafruit UF2 bootloader with SoftDevice S140). Covers the PlatformIO + Adafruit nRF52 Arduino setup for a board that ships in neither, the vendored board definition and Pro Micro pin map, USB CDC via TinyUSB, Bluefruit BLE, the 32.768 kHz crystal that clones omit, SAADC pins, NFC pins as GPIO, and Zephyr's promicro_nrf52840 board target. Use when working on this board or any nice!nano v2 / ZMK keyboard controller: project setup, platformio.ini, pin mapping, LED not blinking, double-tap RESET and UF2/DFU flashing, SoftDevice version mismatches, a board that enumerates but never runs, or debugging why something on the board does not work.
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Firmware development for the Waveshare ESP32-S3-RLCD-4.2 (SKU 33298 / 33507, and the -EN variant) — an ESP32-S3-WROOM-1-N16R8 AIoT board built around a 4.2" fully reflective 300x400 monochrome LCD on a Sitronix ST7305/ST7306, with no backlight, plus an ES8311 speaker codec, an ES7210 dual-microphone ADC, an SHTC3 temperature/humidity sensor, a PCF85063A RTC, a microSD/TF slot on SDMMC, an 18650 holder with battery sensing, BOOT/KEY/PWR buttons and a 2x8 2.54 mm expansion header. Use when working on this board: project setup, platformio.ini, the qio_opi PSRAM memory type, the pin map and which header pins are traps, U8g2 and the ST7305 constructor, a blank or shifted panel, ST7305 low-power mode HPM/LPM, the shared I2C bus and its four slaves, I2S audio directions and the speaker amplifier enable, mounting the TF card, battery voltage, USB CDC console with no UART bridge, flashing over Type-C, deep sleep, or debugging why something on the board does not work.
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Use when designing, reviewing, modifying, migrating, optimizing, securing, operating, troubleshooting, or decommissioning data architectures across data model exploration, SQL, ISO SQL conformance, NoSQL, vector, graph, document, time-series, NewSQL, search, in-memory, SQLite, CDC/Debezium, DBMS storage/query/recovery internals, database incident prevention, hardware acceleration, cache, big-data, lakehouse, and warehouse systems.
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Knowledge base from MIL-HDBK-61B, the DoD Configuration Management (CM) guidance handbook (7 April 2020, cataloged with Change 1, 2025). Use for defense CM across the acquisition and sustainment life cycle: the five CM functions (planning, identification, control/change management, status accounting, verification & audit), the three configuration baselines (FBL/ABL/PBL) and FCD→ACD→PCD documentation, configuration items (CIs/HWCI/CSCI), change instruments (ECP/NOR/RFV), the CCB and Class I/II classification, CDCA/AA authority, FCA/PCA audits, data management and data rights (CDRL/DID, DFARS rights ladder, master/authoritative source), and tailoring CM by phase (EIA-649-1 R/T/NR matrix, Appendix C templates), plus digital-era CM (digital twin, viewpoints, MOSA). NOTE: 61B is advisory guidance that adopts and points to the SAE EIA-649 / EIA-649-1 / GEIA-HB-649 suite for the authoritative CM requirements — this pack names and describes that suite but does not reproduce its copyrighted requirement text. Thin on: the EIA-649 requirement clauses themselves, form-level detail (DD-form field instructions, full DID content), and non-DoD/commercial CM frameworks.
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