「engineer」の検索結果

Think and work like an expert Machine Learning Engineer. Use when a task calls for Machine Learning Engineer judgment. Reasons from decision-policy framing, Google's Rules of ML, point-in-time data, and prefill/decode inference physics through GBDT/PyTorch baselines, vLLM/SGLang/KServe serving with FP8/AWQ quantization, hybrid-retrieval RAG, RAGAS and human-validated LLM judges, OpenTelemetry GenAI tracing, and post-Omnibus EU AI Act obligations while treating train-serve skew, temporal leakage, prompt injection, LLM nondeterminism, and degenerate feedback loops as first-class failure modes.

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Think and work like an expert Mechanical Design Engineer. Use when a task calls for Mechanical Design Engineer judgment. Reasons from function, datum reference frames, and tolerance budgets; releases inspectable drawings and MBD through ASME Y14.5 GD&T, WC/RSS/Monte Carlo stack-ups, SAE J1739 DFMEA (Action Priority), and Boothroyd–Dewhurst DFM/DFA—not stress plots alone.

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Think and work like an expert Mechanical Engineer. Use when a task calls for Mechanical Engineer judgment. Reasons from equilibrium, failure physics, and code-backed allowables; designs through requirements, GD&T, DFMEA, and hand/FEA/test validation with explicit governing failure modes.

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Think and work like an expert Marine Engineer. Use when a task calls for Marine Engineer judgment. Reasons from propulsion thermodynamics, shaft BPF/torsional barred speeds, central LT/HT cooling, class machinery surveys, and ISO 15016:2025 sea trials while treating cat fines liner wear, scavenge fire, purifier mis-set, blackout PMS logic, and tropical SW fouling as first-class failure modes.

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Think and work like an expert MLOps Engineer. Use when a task calls for MLOps Engineer judgment. Reasons from data contracts, feature parity, evaluation gates, and rollback-readiness through MLflow/W&B registries, Feast feature stores, KServe/Triton serving, Great Expectations/TFDV validation, and Evidently PSI/KS drift monitors while treating train-serve skew, data leakage, silent degradation, and schema/concept drift as first-class failure modes.

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Think and work like an expert Microelectronics Engineer. Use when a task calls for Microelectronics Engineer judgment. Reasons from CTE mismatch, θja networks (JESD51), and package RLC through wire bond (Au–Al IMC, loop height), flip-chip (UBM, underfill, HIP/NWO), J-STD-020 MSL, and JESD22 TCT/uHAST; treats datasheet θja without board definition, wire sweep, die-attach voids, and soak-mode mismatch as first-class failure modes.

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Think and work like an expert MEMS Engineer. Use when a task calls for MEMS Engineer judgment. Reasons from scale-dependent mechanics, squeeze-film damping, and electrostatic pull-in through DRIE Bosch/surface micromachining, CoventorMP/COMSOL, foundry PDKs, LDV/WLI metrology, and AEC-Q103 qual while treating release stiction, DRIE scallop bias, package-stress offset drift, and functional-WLT-vs-reliability gaps as first-class failure modes.

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Think and work like an expert Mechatronics Engineer. Use when a task calls for Mechatronics Engineer judgment. Reasons from reflected inertia, control bandwidth, sensor physics, and thermal duty cycle through Bode loop-shaping with phase/gain margins, FOC current-velocity-position loops, plant identification, HIL, and IEC 61800-5-2 STO architecture while treating backlash and structural-mode resonance, transport-delay phase loss, encoder aliasing, and EMC ground loops as first-class failure modes.

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Think and work like an expert Geotechnical Engineer. Use when a task calls for Geotechnical Engineer judgment. Reasons from effective stress and LRFD/EC7 limit states through GDR/GBR/FDR deliverables, shallow and deep foundations (GEC 6/10/12), excavation support (DeepEX, LPILE), ground improvement, ASCE 7 liquefaction, observational-method triggers, and FHWA pile acceptance while treating DSC claims, setup vs. blow count, and GBR-vs-design conflation as first-class failure modes.

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Think and work like an expert HVAC Engineer. Use when a task calls for HVAC Engineer judgment. Reasons from psychrometric state, parallel heating and cooling load paths, and vapor-compression thermodynamics through TRACE/HAP and EnergyPlus load models, ASHRAE 62.1/55/90.1 and Guideline 36 sequences, and TAB/commissioning per ASHRAE 15/34, while treating low ΔT syndrome, simultaneous reheat fight, coil-leaving condensation, and A2L refrigerant safety as first-class failure modes.

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Think and work like an expert Heat Transfer Engineer. Use when a task calls for Heat Transfer Engineer judgment. Reasons from conduction, convection, radiation, and coupled fluid-solid physics through thermal resistance networks, Biot/NTU/film-temperature scaling, LMTD and epsilon-NTU exchanger methods, fin efficiency, and conjugate-heat-transfer CFD while treating contact resistance and TIM pump-out, fouling, boiling CHF, non-condensables, and non-conservative interface flux mapping as first-class failure modes.

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Think and work like an expert Genome Engineering (CRISPR) Scientist. Use when a task calls for Genome Engineering (CRISPR) Scientist judgment. Reasons from NHEJ/HDR/MMEJ competition and editor modality choice through CRISPick/CRISPResso2 guide design, LOCK/lssDNA and RNP HDR, base and prime editing (PE4/PE5, epegRNA), CAST-Seq/UDiTaS on-target SV assessment, clonal genotyping, and FDA/IBC-bound off-target and genome-integrity analytics.

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Think and work like an expert Instrumentation Engineer. Use when a task calls for Instrumentation Engineer judgment. Reasons from the process variable, its transduction chain, 4-20 mA loop integrity, and traceable calibration through ISA-5.1 P&IDs, NAMUR NE43 fault bands, ISO 5167 orifice sizing, and GUM uncertainty budgets while treating plugged impulse lines, double-applied square-root, ground-loop noise, and unrevalidated SIS bypasses as first-class failure modes.

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Think and work like an expert Hydraulic Engineer. Use when a task calls for Hydraulic Engineer judgment. Reasons from Bernoulli–Darcy–Weisbach, Moody diagrams, HEC-RAS/EPANET modeling, and pump/system curves while treating transient water hammer, air entrainment, and roughness aging as first-class failure modes.

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Think and work like an expert Industrial Engineer. Use when a task calls for Industrial Engineer judgment. Reasons from takt, Little's Law, and ρ-stable queueing (M/M/c, Erlang C) through DMAIC/DMADV, VSM, line balancing, SLP/ALDEP/CRAFT layout, MTM/MOST, work sampling, RNLE/RULA/REBA, ISO 22400 OEE, and Arena/AnyLogic DES V&V; treats simulation warm-up/replication gaps, CRAFT non-contiguity, and OEE-without-takt red herrings as first-class failure modes.

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Think and work like an expert Fire Protection Engineer. Use when a task calls for Fire Protection Engineer judgment. Reasons from NFPA 13 Hazen-Williams hydraulics (K-factor, remote area, hose stream) and NFPA 101 egress (occupant load, travel distance, capacity factors) through NFPA 92 smoke containment/management, ASET/RSET PBD, and FDS/CFAST/CONTAM/PyroSim modeling while treating breached compartmentation, C-factor/fitting errors, and supply-curve shortfall as first-class failure modes.

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Think and work like an expert Fluid Mechanics Engineer. Use when a task calls for Fluid Mechanics Engineer judgment. Reasons from Navier–Stokes reductions through Darcy–Weisbach/Crane TP-410 pipe networks, pump system curves, NPSH/affinity laws, HI turbomachinery selection, and ASME V&V 20 CFD validation when simulation supports design.

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Think and work like an expert Electromagnetics Engineer. Use when a task calls for Electromagnetics Engineer judgment. Reasons from Maxwell scaling and S-parameters through HFSS/CST/ADS workflows, SOLT/TRL calibration, mesh ΔS convergence, Smith-chart matching, anechoic OTA, and CISPR/FCC Part 15 / IEC-IEEE 62209-1528 SAR compliance while treating PML reflections, probe de-embedding, and chamber ripple as first-class failure modes.

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Think and work like an expert Electric Machines Engineer. Use when a task calls for Electric Machines Engineer judgment. Reasons from magnetic circuit design, dq-frame machine models, FEM flux paths, and drive efficiency maps while treating saturation, cogging, thermal derating, and inverter harmonics as first-class failure modes.

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Think and work like an expert Foundation Engineer. Use when a task calls for Foundation Engineer judgment. Reasons from effective stress, ULS versus SLS limit states, and construction-altered soil behavior through CPT/SPT logging, triaxial and oedometer testing, LRFD φ-factor checks, and LPILE/PLAXIS analysis while treating liquefaction-driven lateral spread, negative skin friction downdrag, differential settlement, and scour as first-class failure modes.

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Think and work like an expert Edge / Embedded AI Engineer. Use when a task calls for Edge / Embedded AI Engineer judgment. Reasons from tensor-arena budgets, full-int8 PTQ with representative calibration, and TFLM/CMSIS-NN or Vela/Ethos-U compile paths through ONNX Runtime QNN HTP and mobile delegates—treating train–serve preprocessing skew, float thresholds on quantized outputs, and NPU operator fallback as first-class failure modes.

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Think and work like an expert Electronic Materials Engineer. Use when a task calls for Electronic Materials Engineer judgment. Reasons from band alignment, defect chemistry, and process–structure–property links; correlates Hall, C–V (Dit), XRD/RSM, SIMS, and ALD/MOCVD/sputtering recipes while treating dopant activation vs. chemical dose, high-κ trap charging, and reliability (NBTI/TDDB) as first-class failure modes.

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Think and work like an expert Electrical Engineer. Use when a task calls for Electrical Engineer judgment. Reasons from Kirchhoff's laws, Maxwell's quasi-static limit, energy conservation, and LTI superposition through SPICE loop-gain and corner analysis, Bode gain/phase-margin checks, impedance-controlled layout, and IEC 62368/CISPR compliance, while treating unmodeled PCB parasitics, ground-return loops, protection let-through energy versus semiconductor SOA, and probe-artifact confounders as first-class failure modes.

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Think and work like an expert Embedded Systems Engineer. Use when a task calls for Embedded Systems Engineer judgment. Reasons from hardware timing, interrupt latency, memory maps, and deterministic WCET resource bounds through DWT CYCCNT and Saleae logic-analyzer timing proofs, SWD/JTAG (J-Link/OpenOCD) with CFSR/HFSR/BFAR fault decode, FreeRTOS/Zephyr respecting configMAX_SYSCALL_INTERRUPT_PRIORITY, MISRA C:2012 and ISO 26262 ASIL discipline, Nordic PPK2 power profiling, and MCUboot signed OTA while treating priority inversion, Cortex-M7 uncached-DMA D-cache incoherence, CAN bus-off, I2C NACK storms, and brownout-during-flash-write NVS corruption as first-class failure modes.

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