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emulators-debug-log-audit

Parse and interpret execution debug logs generated by the EMULATORS framework, correlating each CPU instruction block with its VIC-II, CIA, SID, interrupt, stop, raster, badline, and memory-access cycles. Use for .LOG traces from EMULATORS when diagnosing cycle timing, raster effects, CPU stalls, IRQ/NMI entry, instruction/chip synchronization, or when reconstructing execution around a PC or mapped register.

Commnets/EMULATORS

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含まれるファイル（4）

SKILL.md3.4 KB
agents/openai.yaml259 B
references/format.md2.7 KB
scripts/analyze_log.py5.9 KB

SKILL.md（原文）

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EMULATORS Debug Log Audit

When compiling or executing an emulator on Windows to produce a log, use $emulators-windows-build-runtime.

Workflow

Inspect the relevant debug... methods before assigning semantics to fields; the log format follows the current implementation.
Run scripts/analyze_log.py LOG --summary first. It streams the file and is suitable for large traces.
Locate relevant code with --match, for example --match 'PC:\$0bd|\$d011|Interrupt'.
Use --before N --after N to preserve CPU-block context. A block is delimited by a line containing only +.
Correlate the CPU header cycle with every chip cycle contained in that block. Expect the number of ordinary VIC-II/CIA cycles to equal the CPU instruction duration, except additional-info records.
Distinguish observation from inference. Report absolute emulator cycles, PC, instruction, raster row/cycle, CPU state, IRQ source/reason, and relevant register values.
For C64 video or CIA conclusions, also use the corresponding VIC-II or CIA audit skill and its reference.

Interpretation Rules

CPU <cycle> Info Cycle opens an instruction-level block. Because debugLastExecutionData runs before the new instruction, Last N cycles describes the preceding instruction, while the following PC line describes the instruction executed in the current block. Compare durations across consecutive instruction blocks, never within the same block.
PC is the instruction address; operand annotations show the effective address and observed/transferred value.
Read numeric CPU states from the current enum before naming them.
Each VICII <cycle> Info Cycle is one recovered cycle. Cross-check ROW/Cycle in Internal with Raster position.
debugVICIICycle records the VIC-II snapshot before that cycle is processed. VIC-II memory-access events occur in the VIC phase; an explicit VIC-II register write record occurs later in the CPU phase of the same absolute cycle. The resulting state normally appears in the next snapshot.
In full-instruction CPU mode, chip cycles are recovered after the CPU instruction has executed. Use the explicit VIC-II register write record to establish the physical bus-write cycle and phase; without that record, do not infer timing from block membership alone.
Treat badline fields, RC, VC, VCBASE, VLMI, DEN and CPU stops as one state machine.
Repeated Interrupt CPU requested records while IRQ remains asserted are not repeated edges. Pair them with wait, rejection and launch records.
Read debugCIACycle and timer accessors before naming every CIA tuple field.
A PC jump alone does not prove an interrupt; require explicit interrupt evidence or vector/stack reconstruction.

Required Output

Provide a compact event timeline, invariants that hold or fail, the earliest divergent cycle, ranked causes with log evidence, and conditional solutions. Do not edit emulator code without explicit authorization.

See references/format.md for provenance and checks.

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c64-1541-audit

無料

Validate Commodore 1540/1541/1541C/1541-II compatible disk-drive behavior in EMULATORS, including IEC serial bus protocol, device numbers, KERNAL traps, CBM DOS commands/status, D64 image parsing, BAM/directory/file chains, PETSCII filenames, 6502 drive CPU/ROM/RAM expectations, 6522 VIA wiring, GCR/track/sector geometry, motor/head timing, and compatibility boundaries for 1541-like devices. Use when Codex reviews or edits C64, VIC-20, C264, COMMODORE disk, serial I/O, D64, CBM DOS, IEC, VIA, GCR, or 1541 drive code.

日本語の概要は準備中です。原文の説明を表示しています。