Document-driven workflow for implementing, reviewing, and verifying Chisel processor and memory-subsystem RTL. Use when Codex must work from maintained Architecture and Design, trace a complete integration surface, reason in synthesized-hardware terms, keep source-adjacent _codex.md summaries current, avoid redundant or overprotective logic, or run focused functional verification.
インストール方法を見るインストールする前に、エージェントに与えられる指示の中身を確認できます。
Read repository instructions first. Then locate and read, in order:
_codex.md summaries, tests, generated reports, and relevant reference implementation.Treat explicit user decisions and the current Git authority as authoritative. Treat a later ordinary user statement as change intent unless the user clearly supersedes an existing fact. Architecture defines target properties, Design defines intended implementation, and Source plus Verification define proven current behavior. Never silently resolve a conflict. State the target, current implementation, evidence, and required migration.
Do not modify Architecture or Design unless the current task authorizes those
edits. Prefer their naming and interface fragments. If a fragment has a syntax,
type, timing, or semantic error, report the exact Design gap before changing its
meaning. Treat a module-local document without the _codex suffix as
human-maintained unless project instructions assign different ownership.
Use $design-chisel-processor when field semantics, ownership lifetime, cycle
boundaries, conflict priority, late-response handling, identity protection, or
acceptance criteria remain unresolved. Begin RTL work only after choices that
affect correctness or interfaces are closed.
Do not repeat questions already answered by the user's latest instruction or accepted documents. Ask before adding a field, protocol, or identity mechanism only when its necessity or semantics remain unresolved. Do not invent unspecified protocols or conservative guards.
Before editing, identify the real elaboration top, source set, immediate dependencies, and downstream regression scope. Search for stale paths, duplicate top-level definitions, and incompatible local copies of shared packages.
For every changed Bundle or protocol, trace definitions, constructors, storage, all producers, all consumers, partial-write methods, tests, widths, encodings, and port order. Separate mechanical ABI migration from semantic redesign. Record which pipeline owns each writable field and which architectural side effects consume it.
Trace a reference implementation through its complete producer-to-consumer path before declaring a local fragment incorrect. Classify each mismatch as design, interface, implementation, documentation, test, or tooling so the correct owner and migration action are explicit.
Read hardware-rules.md before writing RTL.
Make the smallest change that preserves the documented semantics. Reuse the repository's reference processor structure when requested. Keep event generation parallel and centralize state-update priority. Use masks and one-hot selections for candidate networks. Mux only fields consumed on the critical path.
Before each added condition, field, register, or mux, determine whether existing invariants already imply it. Prefer an assertion for an upstream contract over duplicated runtime protection when the design assigns that responsibility upstream.
Organize substantial Scala source with the repository's required functional separators. Add concise comments only for cycle contracts, non-obvious invariants, intentional redundancy left for synthesis, and timing-sensitive choices.
The Agent maintains source-adjacent summaries. Every project-authored .scala
source created or changed by the task must have a same-directory
<SourceBase>_codex.md summary. Create a missing summary and update an existing
summary in the same change. Generated, vendored, and third-party Scala sources
are excluded unless the project explicitly owns them.
Each summary records only implementation-facing facts:
Keep the summary concise and maintainable. It describes the source and cannot
override Architecture or Design. Before delivery, check every changed
project-authored .scala path for its matching summary. The task is incomplete
while any required summary is missing or stale.
Read verification-review.md. Add focused assertions and directed corner cases, then run Verilator as the default ChiselTest backend. Compilation alone is not verification.
For a review-only task, inspect source and documents for correctness, redundancy, overprotection, timing paths, dependency chains, assertion quality, and test gaps without modifying files. For an implementation task, the active Agent owns the edit, focused verification, and final reconciliation.
Dual-subagent verification is disabled by default. Enable it only when the user explicitly requests dual-subagent verification for the current task. Preserve these two independent roles when enabled:
Give both roles source paths, authority documents, the fixed baseline, and
acceptance criteria. Do not give them an expected conclusion. If two independent
subagents are unavailable, report that fact and do not claim independent
verification. The active Agent resolves findings, applies authorized fixes,
reruns affected tests, and updates every affected _codex.md summary.
When an implementation task follows a failed review, address valid findings and rerun affected tests. Review roles report findings without modifying files. Do not report completion while required tests fail.
Report concisely:
_codex.md summaries;まだレビューはありません。使ってみた感想をお寄せください。
概要と使いどころ
Initialize or safely upgrade a processor project's root AGENTS.md from a maintained baseline. Use when starting a processor project, adding project-level Agent collaboration rules, or comparing an existing AGENTS.md with the package baseline. This skill only handles AGENTS.md; it does not scaffold documentation, inspect or configure environments, install tools, or modify processor source.
日本語の概要は準備中です。原文の説明を表示しています。
Develop, challenge, and document Chisel processor microarchitecture designs before implementation. Use when discussing or writing design documents for processor pipelines, queues, issue logic, rename, ROB, LSU, caches, MSHRs, forwarding, wakeup, replay, flush, privilege, exceptions, or other cycle-accurate hardware mechanisms; when converting design conversations into stable Markdown specifications; or when reviewing a proposed Chisel CPU design for correctness, timing, area, verification cost, and cross-document consistency.
日本語の概要は準備中です。原文の説明を表示しています。
Diagnose and optimize timing-critical Chisel RTL for FPGA implementation while preserving cycle semantics. Use for Vivado timing bottlenecks, long ready or admission paths, queue and issue selection, free-list bank mapping, priority encoders, one-hot arbitration, wide muxes, late-arriving forwarding or override data, high-fanout controls, cross-module predicates, register-boundary changes, emitted-Verilog inspection, or routed-DCP A/B analysis. Also use when a source-level simplification needs proof that it changes timing without changing architectural state.
日本語の概要は準備中です。原文の説明を表示しています。
Establish, author, restructure, or audit human-first processor Architecture, Design, Research, Review, and Verification documentation. Use for progressive documentation scaffolding, authority maps, reading paths, document-type content contracts, length-budgeted splitting, or maintainability reviews. Do not use as a substitute for cycle-accurate microarchitecture analysis or RTL implementation.
日本語の概要は準備中です。原文の説明を表示しています。
Task-sized forensic analysis of Vivado synthesis and routed timing evidence for processor RTL. Use when Codex must trace a named setup or hold path, audit whole-design timing populations, compare implementation runs, map primitive, LUT, CARRY, BRAM, DSP, MUXF, register, and routed-net stages back to Chisel or generated RTL, distinguish logic from routing pressure, identify missing DCP queries, or write an evidence-backed timing report. This skill is read-only by default and stops at ranked modification directions. Use optimize-chisel-fpga-timing for RTL edits and routed A/B implementation closure.
日本語の概要は準備中です。原文の説明を表示しています。